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AntonKu
New Contributor
New ContributorFailed to compile project with altlvds with external pll on Cyclone V, Quartus Standard 18.1
Hi, Could anybody give me advise what to do or try? I compile a project with 27 lvds lines running at 384MHz sampling frequency. There is 3 input clocks for each group of 9 lines separately. The re...
AntonKuNew Contributor
New ContributorHi,
I partially solved the issue. To use lvds_serdes hardware, I had to use corner PLLs only and I cannot use the same pll output for Bank 5A and other banks at the same time. There are a few lines in documentation which describe it.
Otherwise the clock (in the end I use the same clock input) is connected to PIN_Y15.
Regards,
Anton
