Error: Port "B" does not exist in primitive "OR2" of instance

component OR2 is

port(A : in std_logic;

Thanks for the prompt response FvM. I tried your suggestion but to no avail.

The problem seems to involve only certain elements of the Altera primitives (AND2, OR2 are both affected) and possibly the libraries in use (ieee, std).

Best Regards

O.K. I see that the mentioned is keyword isn't required, it's no syntax error.

I guess, the problem is either with the port definition in the referenced library, or

because the component name interfers with another library. This can't be determinded

without seeing the complete code, including the use library statements.

From the sounds of it, you have a missmatch in the port definition of the component of OR2 and the actual entity of OR2. If you look at the entity definition of OR2, I bet it doesnt have A as a port.

This is one reason why component declarations are annoying, and since VHDL 1993, pretty pointless if you have the source code for OR2. You have to maintain the same thing in 2 different places, and if you update the entity, but forget to update the component, you get this error.

you can instantiate OR2 directly so that the compiler will pick up any port missmatch errors rather than the synthesisor/simulator. To do direct instantiation, delete your compoenent declaration, and use the following when you want an instance of OR2.

reset_or : entity (my_library).OR2 port map ( 

my_library is the library OR2 exists in - if it is in the same library as the current project you can use work instead. But if OR2 comes from another source (like AHDL or verilog) or is a black box, you have to retain the component declaration.

How do I find out which library contains the OR2 entity?

Is there some library supplied with Quartus that contains so-called 'primitives' like OR2?

The only files I can find that contain 'OR2' are in the C:\altera\90sp2\quartus\libraries\primitives\logic directory.

These files, (e.g. or2.bsf), do not appear to contain entity definitions.

If I want to have an OR2 component to use in my design, do I have to make it myself ( explicitly define the entity port map, architecture, etc )?

why not just write it out in VHDL? or are you sure you want to use a structural load of VHDL at a very low level?

if you're not, just do this:

IReset <= Qaux(11) or Reset;

My design was developed in a different environment. The VHDL design files from that environment contain dozens of instantiations of OR2, AND2, OR3, etc. Therefore, without a major edit, I cannot use inline statements ( OutSig <= InSig1 or InSig2).

I created a new file (primitives.vhd) and put in the following code:

library ieee;

use ieee.std_logic_1164.all;

entity OR2 is

port(A, B : in std_logic; Y : out std_logic);

end OR2;

architecture DEF_ARCH of OR2 is

begin

Y <= A or B;

end DEF_ARCH;

I added this new file to the project and tried to compile. I get these errors:

Error: Port "A" does not exist in primitive "OR2" of instance "Reset_OR"

Error: Port "B" does not exist in primitive "OR2" of instance "Reset_OR"

Error: Port "Y" does not exist in primitive "OR2" of instance "Reset_OR"

Now, if I change the name of the entity in my primitives.vhd file from OR2 to MOR2:

entity MOR2 is

port(A, B : in std_logic; Y : out std_logic);

end MOR2;

architecture DEF_ARCH of MOR2 is

begin

Y <= A or B;

end DEF_ARCH;

and change the instantiation accordingly:

Reset_OR : MOR2 port map(A => Reset,

B => Qaux(11),

Y => IReset);

It then compiles this component without errors and continues to the next error.

This suggests that indeed there is some primitive "OR2" defined somewhere that interferes with my explicitly defined entity named OR2.

Where are these primitive entities located and defined?

Best Regards

I cannot find an OR2 component in any of the altera librarys. I can only find functions and prodecuders associated named things like VitalOR2, but thats not relevent.

Either they are from a custom package or maybe they are Xilinx?

try something like this:

library ieee;
use ieee.std_logic_1164.all;
entity mytest is
port(
pina : in std_logic;
pinb : in std_logic;
pinc : out std_logic);
end mytest;
architecture RTL of mytest is
component OR2
port(IN1 : in std_logic;
IN2 : in std_logic;
\OUT\ : out std_logic);
end component;
begin
    --testOR2 : OR2 port map(pina, pinb, pinc);
    testOR2 : OR2 port map(IN1 => pina, IN2 => pinb, \OUT\ => pinc);
end RTL;