Error: Port "B" does not exist in primitive "OR2" of instance

My design was developed in a different environment. The VHDL design files from that environment contain dozens of instantiations of OR2, AND2, OR3, etc. Therefore, without a major edit, I cannot use inline statements ( OutSig <= InSig1 or InSig2).

I created a new file (primitives.vhd) and put in the following code:

library ieee;

use ieee.std_logic_1164.all;

entity OR2 is

port(A, B : in std_logic; Y : out std_logic);

end OR2;

architecture DEF_ARCH of OR2 is

begin

Y <= A or B;

end DEF_ARCH;

I added this new file to the project and tried to compile. I get these errors:

Error: Port "A" does not exist in primitive "OR2" of instance "Reset_OR"

Error: Port "B" does not exist in primitive "OR2" of instance "Reset_OR"

Error: Port "Y" does not exist in primitive "OR2" of instance "Reset_OR"

Now, if I change the name of the entity in my primitives.vhd file from OR2 to MOR2:

entity MOR2 is

port(A, B : in std_logic; Y : out std_logic);

end MOR2;

architecture DEF_ARCH of MOR2 is

begin

Y <= A or B;

end DEF_ARCH;

and change the instantiation accordingly:

Reset_OR : MOR2 port map(A => Reset,

B => Qaux(11),

Y => IReset);

It then compiles this component without errors and continues to the next error.

This suggests that indeed there is some primitive "OR2" defined somewhere that interferes with my explicitly defined entity named OR2.

Where are these primitive entities located and defined?

Best Regards