Error: Port "B" does not exist in primitive "OR2" of instance

From the sounds of it, you have a missmatch in the port definition of the component of OR2 and the actual entity of OR2. If you look at the entity definition of OR2, I bet it doesnt have A as a port.

This is one reason why component declarations are annoying, and since VHDL 1993, pretty pointless if you have the source code for OR2. You have to maintain the same thing in 2 different places, and if you update the entity, but forget to update the component, you get this error.

you can instantiate OR2 directly so that the compiler will pick up any port missmatch errors rather than the synthesisor/simulator. To do direct instantiation, delete your compoenent declaration, and use the following when you want an instance of OR2.

reset_or : entity (my_library).OR2 port map ( 

my_library is the library OR2 exists in - if it is in the same library as the current project you can use work instead. But if OR2 comes from another source (like AHDL or verilog) or is a black box, you have to retain the component declaration.