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Altera_Forum
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16 years ago

Error: Port "B" does not exist in primitive "OR2" of instance

When attempting to compile the following code in Quartus entity Pulse_Gen is port(Clock : in std_logic; Reset : in std_logic; PulseOut : out std_logic); end Pulse_Ge...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

try something like this: 

library ieee;
use ieee.std_logic_1164.all;
entity mytest is
port(
pina : in std_logic;
pinb : in std_logic;
pinc : out std_logic);
end mytest;
architecture RTL of mytest is
component OR2
port(IN1 : in std_logic;
IN2 : in std_logic;
\OUT\ : out std_logic);
end component;
begin
    --testOR2 : OR2 port map(pina, pinb, pinc);
    testOR2 : OR2 port map(IN1 => pina, IN2 => pinb, \OUT\ => pinc);
end RTL;