Easiest Testbench for my VHDL code (multiplication)

Thanks a lot for these files.. But i don't know what to write to UUT.. It is empty and i need to put values there.

I need testbench.. It is school homework but i don't know how to edit it.

Hi

--ONE OF THE WAY OF WRITING TB IS SHOWN YOU CAN USE LOOPS TO TEST ALL THE CASE
  stimulus: process
  begin
    a<="0101";
    b<="0101";
    wait for 20ns;
    a<="1111";
    b<="1111";
    wait;
  end process;

--ONE OF THE WAY OF WRITING TB IS SHOWN YOU CAN USE LOOPS TO TEST ALL THE CASE
  stimulus: process
  begin
    a<="0101";
    b<="0101";
    wait for 20ns;
    a<="1111";
    b<="1111";
    wait;
  end process;

# ** Error: D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd(96): near "'": syntax error# ** Error: D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd(97): near "'": syntax error#  ** Error: D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd(98): near "'": syntax error#  ** Error: D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd(100): near "'": syntax error#  ** Error: D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd(104): VHDL Compiler exiting#  ** Error: D:/altera/13.0sp1/modelsim_ase/win32aloem/vcom failed.

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity nasobenie_tb is
generic
  	(
  		DATA_WIDTH : natural := 4
  	);
end;
architecture bench of nasobenie_tb is
  component nasobenie
  	generic
  	(
  		DATA_WIDTH : natural := 4
  	);
  	port 
  	( 
  		a	   : in signed ((DATA_WIDTH-1) downto 0);
  		b	   : in signed ((DATA_WIDTH-1) downto 0);
  		q  : out signed ((2*DATA_WIDTH-1) downto 0)
  	);
  end component;
  signal a: signed ((DATA_WIDTH-1) downto 0);
  signal b: signed ((DATA_WIDTH-1) downto 0);
  signal q: signed ((2*DATA_WIDTH-1) downto 0) ;
begin
  -- Vlozenie hodnot pre parameter generic !!
  uut: nasobenie generic map ( DATA_WIDTH => DATA_WIDTH )
                          port map ( a          => a,
                                     b          => b,
                                     q     => q );
  stimulus: process
  begin
 a <= '0000';
   b <= '0000';
   wait for 10 ns;
   assert(q = '00000000');
   a <= '0001';
   b <= '0000';
   wait for 10 ns;
   assert(q = '00000000');
	a <= '0010';
   b <= '0000';
   wait for 10 ns;
   assert(q = '00000000');
	a <= '0011';
   b <= '0000';
   wait for 10 ns;
   assert(q = '00000000');
	a <= '0100';
   b <= '0000';
   wait for 10 ns;
   assert(q = '00000000');
	a <= '0101';
   b <= '0000';
   wait for 10 ns;
   assert(q = '00000000');
	a <= '0110';
   b <= '0000';
   wait for 10 ns;
   assert(q = '00000000');
	a <= '0111';
   b <= '0000';
   wait for 10 ns;
   assert(q = '00000000');
	a <= '1000';
   b <= '0000';
   wait for 10 ns;
   assert(q = '00000000');
	a <= '1001';
   b <= '0000';
   wait for 10 ns;
   assert(q = '00000000');
	a <= '1010';
   b <= '0000';
   wait for 10 ns;
   assert(q = '00000000');
	a <= '1011';
   b <= '0000';
   wait for 10 ns;
   assert(q = '00000000');
	a <= '1100';
   b <= '0000';
   wait for 10 ns;
   assert(q = '00000000');
	a <= '1101';
   b <= '0000';
   wait for 10 ns;
   assert(q = '00000000');
	a <= '1111';
   b <= '0000';
   wait for 10 ns;
   assert(q = '00000000');
	end process; --koniec opisu procesov
 end bench; --koniec opisu architektury tb
configuration cfg_bench of nasobenie_tb is --konfiguracia test bench entity
   for bench --cyklus je prazdny, nema ziadnu specificku funkciu v nasom pripade
   end for; --koniec cyklu
end cfg_bench; --koniec opisu konfiguracie

for strings (like arrays) you should be using double quotes, not single quotes.

Thanks for help. One more problem:

# ** Fatal: (vsim-3420) Array lengths do not match. Left is 4 (3 downto 0). Right is 2 (3 downto 2).
#     Time: 0 ps  Iteration: 0  Process: /nasobenie_tb/stimulus File: D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd
#  Fatal error in Process stimulus at D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd line 41
#  
#  HDL call sequence:
#  Stopped at D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd 41 Process stimulus
#  

I think the error is fairly self explanitory.

It is multiplication.. When i multiply 2 bits and 2 bits number, result is 4 bits or i am wrong?

Yes, multiplying 2 bit numbers gives a 4 bit result.