Easiest Testbench for my VHDL code (multiplication)

Thanks for help. One more problem:

# ** Fatal: (vsim-3420) Array lengths do not match. Left is 4 (3 downto 0). Right is 2 (3 downto 2).
#     Time: 0 ps  Iteration: 0  Process: /nasobenie_tb/stimulus File: D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd
#  Fatal error in Process stimulus at D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd line 41
#  
#  HDL call sequence:
#  Stopped at D:/altera/13.0sp1/nasobenie/nasobenie_tb.vhd 41 Process stimulus
#