duplicate design

Hi odedidush.

Yes. You have to use your design as a component and instantiate n times. You use the old top level entity as a component in another vhdl file.

For generate is like an automatic copy+paste:

name: for i in 0 to 7 generate

somename_unit : yoursystem port map

(... -- instantiation

)

end generate name;

Hi bertulus , i have some more questions .

i understand from you that i need to instantiate all the ports of the current Top file from another vhdl file .

do i instantiate the ports same as i instantiate it from the Test Bench ? what about the signals , do i need to instantiate them as well at the vhdl file ?

The design have one input clock at Freq=125MHz and it's connected to PLL that has two output at c0=25MHz and c1=100MHz .

if i create a new file with more similar components, will it be better to take the PL outL from the current top file and put it at the new vhdl file?

then the PLL will spread the c0,c1 to all new components .

the second option is to stay at this situation when the PLL is inside every component but then the design can have large number of PLL's .

i added the current Top file .

Thanks for your advice .

I understand top.vhd is the black box you need to replicate. I don't place a pll on every unit I have to instantiate. First, because the global circuit will have many clocks. If the unit have to communicate each other, they have different clock domain. You can avoid it. Second, you have a small numbers of pll in a fpga ( depends of the device ).

If I found in my hard disk, i post the code of an iterative circuit ( an incrementor ) made of a simple unit, replied N times. It's a good example of how to use for generate.

Hi bertulus ,

i did as you said , i duplicate the black box N times with all input and output ports .

about the clocks , the issue is that there is one clock input to the design and i used 1 PLL at the new vhd file.

The PLL has 2 output - c0,c1 that connected to each black box ,

The design has more than one black box and need to connect the PLL outputs (C0,C1) to each one of them .

i defined 2 signals of std_logic_vectors(1 downto 0) - PLL_lock_25M,PLL_lock_100M and connect them at the for generate loop :

dup : for i in 1 to 2 generate

one: Design port map

(

clk_in_25M => PLL_lock_25M(i-1)

clk_in_100M => PLL_lock_100M(i-1)

...

)

end generate ;

at the PLL instantiation i wrote :

pll1: entity.pll (behave) ... port map (

c0 => PLL_lock_25M

c1 => PLL_lock_100M

...

);

after compilation there is error at this section because c0,c1 are std_logic and PLL_lock_25M,PLL_lock_100M are std_logic_vector and the instantiation doesn't succeed .

what do you recommend to do ?

The clock should be std_logic, no std_logic_vector:

signal PLL_lock_25M,PLL_lock_100M : std_logic;

dup : for i in 1 to 2 generate

one: Design port map

(

clk_in_25M => PLL_lock_25M,

clk_in_100M => PLL_lock_100M

...

)

end generate ;

at the PLL instantiation i wrote :

pll1: entity.pll (behave) ... port map (

c0 => PLL_lock_25M

c1 => PLL_lock_100M

...

);

Hi bertulus ,

i did as you said and define the clk_in and pll_25M_out, pll_100M_out as std_logic .

i publish the full new .vhd file that i create in order to duplicate the PRBS box . i also publish the design scheme at word file .

---------------------------------------------------------------------------------------

-- Top Design

library ieee;

use ieee.std_logic_1164.all;

entity TopDesign is

port(

clk_in : in std_logic;

ser_in1 : in std_logic;

lock_out : out std_logic;

ser_out : out std_logic

);

end entity TopDesign;

architecture Design of TopDesign is

signal pll_25M_out : std_logic; -- 25M output from PLL

signal pll_100M_out : std_logic; -- 100M output from PLL

signal PLL_locked : std_logic; -- when PLL_Locked = '0' it send resetN ='0' to all components

signal ResetN_25M : std_logic;

signal ResetN_100M : std_logic;

--signal debug_clk_in_test : std_logic;

begin

--The PLL instantiation is :

Top_level_pll: entity work.pll_125M (SYN)

port map(

inclk0 => clk_in , --in std_logic

c0 => pll_25M_out , --out std_logic

c1 => pll_100M_out, --out std_logic

locked => PLL_locked --out std_logic

);

Top_level_Meta_Reset_25M: entity work.Meta_Reset (behave)

port map(

locked => PLL_locked, --in std_logic

clk => pll_25M_out, --in std_logic

Din => '1' , --in std_logic

rst_n=> ResetN_25M --out std_logic

);

Top_level_Meta_Reset_100M: entity work.Meta_Reset (behave)

port map(

locked => PLL_locked, --in std_logic

clk => pll_100M_out, --in std_logic

Din => '1' , --in std_logic

rst_n=> ResetN_100M --out std_logic

);

--The duplicate PRBS box instantiation is :

Top_level_Top: for i in 1 to 2 generate

duplicate:entity work.top(Design)

port map(

clk_in1=>pll_25M_out, --in std_logic

clk_in2=>pll_100M_out, --in std_logic

ResetN_25M => ResetN_25M, --in std_logic

ResetN_100M => ResetN_100M, --in std_logic

ser_in1 => ser_in1, --in std_logic

ser_out => ser_out, --out std_logic

lock_out => lock_out --out std_logic

);

end generate ;

end architecture Design;

------------------------------------------------------------------------------------------

After the simulation at Model Sim the signals and prots of top entity duplicate ( Top_level_Top(1) , Top_level_Top(2) ) .

i tried to use the duplicated ports at Quartus Pin Planner, F.E : ser_in1(2),ser_out(2) and the Quartus didn't find them .

i just want to be clear , as mentioned at the scheme , the topddesign have n ser_in1 input ports , n ser_out output ports and n lock_out outputs ports .

don't i need to define the inputs , outputs as std_logic _vector in order that Quartus will know that its more that one pin ?

in this situation does the input for every entity (i.e Resets, clocks ...) should be std_logic _vector as well ?

Thanks .

According to the word document you should not declare clock and resets as vector because are the same clock and reset for all instantiated modules. It's the same wire. But Ser_out and ser_in must be vector. Something like:

signal ser_in1 : std_logic_vector(1 downto 0);

signal ser_out : std_logic_vector(1 downto 0);

signal lock_out : std_logic_vector(1 downto 0);

Top_level_Top: for i in 1 to 2 generate

duplicate:entity work.top(Design)

port map(

clk_in1=>pll_25M_out, --in std_logic

clk_in2=>pll_100M_out, --in std_logic

ResetN_25M => ResetN_25M, --in std_logic

ResetN_100M => ResetN_100M, --in std_logic

ser_in1 => ser_in1(i - 1), --in std_logic

ser_out => ser_out(i -1), --out std_logic

lock_out => lock_out(i - 1) --out std_logic

);

Thanks a lot bertulus ,

i changed the code and the design work properly at simulation and after synthesis and burning the code to evaluation board .