Honored Contributor
Honored ContributorI understand top.vhd is the black box you need to replicate. I don't place a pll on every unit I have to instantiate. First, because the global circuit will have many clocks. If the unit have to communicate each other, they have different clock domain. You can avoid it. Second, you have a small numbers of pll in a fpga ( depends of the device ).
If I found in my hard disk, i post the code of an iterative circuit ( an incrementor ) made of a simple unit, replied N times. It's a good example of how to use for generate.
