duplicate design

Hi bertulus , i have some more questions .

i understand from you that i need to instantiate all the ports of the current Top file from another vhdl file .

do i instantiate the ports same as i instantiate it from the Test Bench ? what about the signals , do i need to instantiate them as well at the vhdl file ?

The design have one input clock at Freq=125MHz and it's connected to PLL that has two output at c0=25MHz and c1=100MHz .

if i create a new file with more similar components, will it be better to take the PL outL from the current top file and put it at the new vhdl file?

then the PLL will spread the c0,c1 to all new components .

the second option is to stay at this situation when the PLL is inside every component but then the design can have large number of PLL's .

i added the current Top file .

Thanks for your advice .