duplicate design

Hi bertulus ,

i did as you said , i duplicate the black box N times with all input and output ports .

about the clocks , the issue is that there is one clock input to the design and i used 1 PLL at the new vhd file.

The PLL has 2 output - c0,c1 that connected to each black box ,

The design has more than one black box and need to connect the PLL outputs (C0,C1) to each one of them .

i defined 2 signals of std_logic_vectors(1 downto 0) - PLL_lock_25M,PLL_lock_100M and connect them at the for generate loop :

dup : for i in 1 to 2 generate

one: Design port map

(

clk_in_25M => PLL_lock_25M(i-1)

clk_in_100M => PLL_lock_100M(i-1)

...

)

end generate ;

at the PLL instantiation i wrote :

pll1: entity.pll (behave) ... port map (

c0 => PLL_lock_25M

c1 => PLL_lock_100M

...

);

after compilation there is error at this section because c0,c1 are std_logic and PLL_lock_25M,PLL_lock_100M are std_logic_vector and the instantiation doesn't succeed .

what do you recommend to do ?