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Altera_Forum
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12 years ago

duplicate design

Hi , At my project i design system that generate PRBS data and lock at the transmiter PRBS data . i used 11 files for the components of the design and after simulation ,synthesis and burning th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi odedidush.

Yes. You have to use your design as a component and instantiate n times. You use the old top level entity as a component in another vhdl file.

For generate is like an automatic copy+paste:

name: for i in 0 to 7 generate

somename_unit : yoursystem port map

(... -- instantiation

)

end generate name;