duplicate design

According to the word document you should not declare clock and resets as vector because are the same clock and reset for all instantiated modules. It's the same wire. But Ser_out and ser_in must be vector. Something like:

signal ser_in1 : std_logic_vector(1 downto 0);

signal ser_out : std_logic_vector(1 downto 0);

signal lock_out : std_logic_vector(1 downto 0);

Top_level_Top: for i in 1 to 2 generate

duplicate:entity work.top(Design)

port map(

clk_in1=>pll_25M_out, --in std_logic

clk_in2=>pll_100M_out, --in std_logic

ResetN_25M => ResetN_25M, --in std_logic

ResetN_100M => ResetN_100M, --in std_logic

ser_in1 => ser_in1(i - 1), --in std_logic

ser_out => ser_out(i -1), --out std_logic

lock_out => lock_out(i - 1) --out std_logic

);