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Altera_Forum's avatar
Altera_Forum
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16 years ago

Domain crossing of related clocks

I have been trying to figure out how to constrain a path of data between a 100MHz clock and a 25MHz clock that is generated by counter driven by the 100MHz clock.

I have tried

#set_multicycle_path -start -from [get_clocks CLOCK100M] -to [get_clocks CLOCK25M] 3

and

#set_max_delay -from [get_clocks CLOCK100M] -to [get_clocks CLOCK25M] 30.000

but I am getting hold errors.

If I add# set_min_delay -from [get_clocks CLOCK100M] -to [get_clocks CLOCK25M] -5.000

this removes the hold errors but how can I have a negative hold delay?

I am very confused and could use some help.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I'm not sure you need to do anything actually. As long as the two clocks are in the same group and no false path have been specified between the two domains, Timequest should check the setup/hold violations in the worst cases.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    This is what I see if I don't constrain the crossing.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I'm not an expert in Timequest, but I'd say that the long delay on the 25MHz clock is due to the fact that you use a counter to generate it, and it will be difficult to reduce without a pll.

    The only way to pass the timing requirements without changing the design would be to use a negative hold time, as you did. But I would also specify a negative max delay to be sure it remains that way on all the temperature range. I don't see any problem with negative hold delays in this case.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The trick is to get Quartus to use the right edges. I have a similar situation with a PLL phase shift. Try using separate setup and hold constraints. Normally you would set the hold requirement one less than the setup but in this case setting them equal may work better. I haven't tried these but experiment with different values and see what you get.

    set_multicycle_path -start -from [get_clocks CLOCK100M] -to [get_clocks CLOCK25M] -start -setup 3

    set_multicycle_path -start -from [get_clocks CLOCK100M] -to [get_clocks CLOCK25M] -start -hold 3
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Sounds like it would be much easier if you drove everything off the 100MHz clock and use the 25Mhz generated clock as Enables to those registers you want to be in the 25MHz domain. :)

    Cheers,

    Thean Charn