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Altera_Forum
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16 years ago

Domain crossing of related clocks

I have been trying to figure out how to constrain a path of data between a 100MHz clock and a 25MHz clock that is generated by counter driven by the 100MHz clock. I have tried #set_mult...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The trick is to get Quartus to use the right edges. I have a similar situation with a PLL phase shift. Try using separate setup and hold constraints. Normally you would set the hold requirement one less than the setup but in this case setting them equal may work better. I haven't tried these but experiment with different values and see what you get.

set_multicycle_path -start -from [get_clocks CLOCK100M] -to [get_clocks CLOCK25M] -start -setup 3

set_multicycle_path -start -from [get_clocks CLOCK100M] -to [get_clocks CLOCK25M] -start -hold 3