Domain crossing of related clocks

I'm not an expert in Timequest, but I'd say that the long delay on the 25MHz clock is due to the fact that you use a counter to generate it, and it will be difficult to reduce without a pll.

The only way to pass the timing requirements without changing the design would be to use a negative hold time, as you did. But I would also specify a negative max delay to be sure it remains that way on all the temperature range. I don't see any problem with negative hold delays in this case.