Does the Agliex F support Display port IP ?

Hi Liang Hong,

Thank you for reaching out.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

Allow me some time to look into your issue. I shall come back to you with findings.

Thank you for your patience.

Best Regards,

ZulsyafiqH_Intel

Hi Liang Hong,

Apologize for the delayed response.

For Agilex device, currently we only have 2 design example available in Quartus software as below:

Table 3. DisplayPort Intel FPGA IP Design Example Parameters for Intel Agilex F-tile Device

For DisplayPort SST Parallel Loopback without PCR design, you are required to turn on the Enable Video Input Image Port parameter to be able to view the design in the "select design" dropdown list under the design example tab.

As for DisplayPort SST Parallel Loopback with AXIS Video Interface, you are required to set Enable Active Video Data Protocols to AXIS-VVP Full for both DisplayPort Sink and Source option in the IP tab to be able to view the design.

You may refer to below link for your reference:

F-Tile DisplayPort Intel® FPGA IP Design Example User Guide - 1.6. DisplayPort Intel® FPGA IP Design Example Parameters

Q1.Did you enable/turn on the parameter settings as above?

Q2.May I know which OPN and Quartus version that you are using?

Q3.May I know which design example you are trying to generate?

Thank you.

Best Regards,

ZulsyafiqH_Intel

Hi Liang Hong,

Thank you for your feedback.

As mentioned for DisplayPort SST Parallel Loopback with AXIS Video Interface, please make sure you change the

"Enable Active Video Data Protocols" parameter to "AXIS-VVP Full" for both DisplayPort Sink and Source in the IP tab to be able to view the example design.

IP Parameter editor screenshot(1)

IP Parameter editor screenshot(2), (Scroll down the IP tab, you can find settings for Sink)

Once you change both Source and Sink "Enable Active Video Data Protocols" parameter to "AXIS-VVP Full", you will be able to see as below:

Design Example Tab

Hope this answers your question.

Thank you.

Best Regards,

ZulsyafiqH_Intel

Hi

Yes, when we turn-on the AXISWP on TX and RX. An example will be created.

but P&R this example will error

and

we don't know how to regenerate the F-tile IP. it seems a predesign IP manually from the Example.

BR

Hong

Hi Liang Hong,

Thank you for your reply.

I have checked and generated a design example from my end and I do not observe any error in compilation.

Allow me to share with you my design for you to test from your end.

Q1. Did you change any setting in the Design example?

Q2. Do you mind sharing the steps/procedure that you use to generate the design example?

Thank you.

Best Regards,

ZulsyafiqH_Intel

Hi Liang Hong,

We have not heard feedback from you for about a week.

I wish to follow up with you on this Case.

I would like to get update on my previous reply.

Did you manage to run the design I shared?

Do you still have further inquiries on this case?

If there is no further inquiries, , I will transition this thread to community support.

Thank you.

Best Regards,

ZulsyafiqH_Intel

Hi Liang Hong,

We did not receive any response from you for about 2 weeks with regards to the reply that I have provided.

With that, this thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Stay safe, and I hope you have a great day.

Thank you.

Best Regards,

ZulsyafiqH_Intel