design a BCD Counter

Hi Gabra, sorry say this but I fear you need grasp digital design in deep as i usually told my pupils, error come from everywhere.

A BCD counter never count to 1010 that is ten decimal but remain in BCD domain {0..9} .

You can apply this method to ripple carry asyncronous reset but not to a syncronous counter as your appear to be.

This case require an enable count that happen on last digit value, when counter is 9 then load 0 as next state, at same time enable count on next digit. Your design miss this feature.

I suggest you start learning an HDL language and do this in a more simple fashion using state machine. I am proficient on VHDL and just read and understand Verilog I don't like so much, in HDL your design can be:

signal BCD : Std_Logic_Vector(3 downto 0);
 
 signal enable : Std_Logic := '1'; -- enable count
 
signal sreset : std logic := '0'; -- reset to 0 clock gated
 
 
 
BCD_counter: process (clock, reset_n)
 
var count : integer range 0 to 9 := 0;
 
if reset_n = '0' then
 
 count := 0; -- async reset
 
else
 
 If rising_edge(clock, reset_n) then
 
BCD <= Std_Logic_Vector(to_unsigned(count, 4));
 
if enable = '1' then
 
 if count = 9 or sreset = '1' then
 
 Count := 0;
 
else
 
 count := count +1;
 
end if; -- counter
 
end if; -- enable
 
end if; -- edge
 
end if; -- reset
 
end process;
 

Regards

Sorry for misunderstood, here we are professional seeking for "Exchange" or hint, didn't mean you are useless nor wrong, you welcome but just too early to interact here.

I was trying say to you this channel is wrong for learning when at too basic level, I suggested you college channel where you can interact other pupils and learn from what we teach.

Remember I am not paid to teach for free nor other can do and never we can do homework for free, this sound as stopping teacher/professional work like me or colleague at other sides.

(ZEN) Also it is useless and bad to criticize your lecturer, in my point of view still is a colleague and when you as pupils do a criticism to my colleague I can think you do same for me...

Sometimes I see some my colleague perform bad but remember deontological ethics tell me to not confirm and forever protect them in front of an attack right or odd. (IEEE rule too)

Also please be coherent, I sent you a couple of link where you can find help, Pyroedu and FPGA4Fun both have teaching materials and discussion on how to build counters, Deeds site devoted to teaching has material on topics.

Both book and course too start from Logic gates, they use a special (free) tool customized for teaching Logic design.

What is wrong with lecturer or pupils has to be left behind your college, please avoid do it in public, at least do in PM.

Regards