New Contributor
New Contributori found what was wrong. as @RRomano001 suggested. i had my most and lest significant bits switched, that's why it wasn't right. But now i'm trying to expand it into a digit counter by adding wires from Not Q[0], Q[1], Not Q[2] and Q[3] connected to AND4 logic gate so that when we get 1010 it will feed into the next counter and give us the next digit which is not doing so. i'm thinking it's the wire placement that is wrong. do you have any idea where to add them
thank you
ContributorHi Gabra, sorry say this but I fear you need grasp digital design in deep as i usually told my pupils, error come from everywhere.
A BCD counter never count to 1010 that is ten decimal but remain in BCD domain {0..9} .
You can apply this method to ripple carry asyncronous reset but not to a syncronous counter as your appear to be.
This case require an enable count that happen on last digit value, when counter is 9 then load 0 as next state, at same time enable count on next digit. Your design miss this feature.
I suggest you start learning an HDL language and do this in a more simple fashion using state machine. I am proficient on VHDL and just read and understand Verilog I don't like so much, in HDL your design can be:
signal BCD : Std_Logic_Vector(3 downto 0);
signal enable : Std_Logic := '1'; -- enable count
signal sreset : std logic := '0'; -- reset to 0 clock gated
BCD_counter: process (clock, reset_n)
var count : integer range 0 to 9 := 0;
if reset_n = '0' then
count := 0; -- async reset
else
If rising_edge(clock, reset_n) then
BCD <= Std_Logic_Vector(to_unsigned(count, 4));
if enable = '1' then
if count = 9 or sreset = '1' then
Count := 0;
else
count := count +1;
end if; -- counter
end if; -- enable
end if; -- edge
end if; -- reset
end process;
Regards
