Forum Discussion
New Contributordesign a BCD Counter
ContributorHi, I got eye on it.
Compile to 2 LE so a lot of design error can be on it or I am wrong , I don't use schematic nor Cyclone IV so may be some setting where lost on conversion.
When you have your lecturer again on lab, show the link I sent to you, may be it find more useful than try use Quartus in Archaic mode.
BCD Counter still have trouble, ripple counter clock are to be avoided on FPGA, enable is missing and also next counter has to increment from 9 to 0 transition not from 0 to 1.
BCD decoder has more sense on output multiplexer than on every digit, this is not a big issue. Just use one at output where you drive multiplexed display.
Note: may be synthesis do it for you, but you have to learn good practice.
An LED display don't like to be driven @50/4-> 12.5MHz so reduce to a reasonable frequency, scale clock to 10KHz or less.
I see you didn't grasped enough logic design, try use DEEDS I suggested, you can single step clock and see every point of the circuit probing level or display value all in real time. This is targeted to learn digital design @college and high school too.
Tool export design to Altera Quartus and selected board, enjoy it.
Your design required 44 second to compile, I fear on a non Linux or MAC took some minutes so this waste a lot of time.
Sorry I cannot debug your homework, you need use a good textbook, if still available at Logic gate time I adopted Floyd Digital design, old book
https://www.amazon.com/Digital-Fundamentals-Global-FLOYD-THOMAS/dp/1292075988/ref=dp_ob_title_bk
If you are at college course Deeds book is more close:
browse college site and subscribe to, you may get more help than where we are busy with deadline of release project.
Regards.
gabra4Hello. Thank you for all your assistance. I do appreciate it. I know my knowledge is limited in this subject and my methods are primitive, but as long as it shows correctly on the fpga i will get full mark. My biggest problem is that my lecturer is bad at teaching, he knows everything so he thinks we all should know it too. If i compare this subject to driving a car, what he does is teching us how to build car parts and then asking us to drive it. See where i'm going with that. I can't even ask classmates for help because i'm the one who knows more than everyone. My test is next monday and he demands us to do stuff never mentioned in the lecture, like how to build a bcd counter with a parallel load, i tried googling it but as you said, no one use schematics while we are forced to use it. Anyway, i'm definitely getting a 70% mark on that project which is nice. Also i would like to thank you for your time trying to help me even though i'm useless lol.
- RRomano001
Sorry for misunderstood, here we are professional seeking for "Exchange" or hint, didn't mean you are useless nor wrong, you welcome but just too early to interact here.
I was trying say to you this channel is wrong for learning when at too basic level, I suggested you college channel where you can interact other pupils and learn from what we teach.
Remember I am not paid to teach for free nor other can do and never we can do homework for free, this sound as stopping teacher/professional work like me or colleague at other sides.
(ZEN) Also it is useless and bad to criticize your lecturer, in my point of view still is a colleague and when you as pupils do a criticism to my colleague I can think you do same for me...
Sometimes I see some my colleague perform bad but remember deontological ethics tell me to not confirm and forever protect them in front of an attack right or odd. (IEEE rule too)
Also please be coherent, I sent you a couple of link where you can find help, Pyroedu and FPGA4Fun both have teaching materials and discussion on how to build counters, Deeds site devoted to teaching has material on topics.
Both book and course too start from Logic gates, they use a special (free) tool customized for teaching Logic design.
What is wrong with lecturer or pupils has to be left behind your college, please avoid do it in public, at least do in PM.
Regards
