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gabra4's avatar
gabra4
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7 years ago

design a BCD Counter

hello. i'm a bit of a newbie here and i'm trying to create a bcd counter schematic for a university project using either a tff or a dff. i created the truth table for the circuit and designed the ci...
RRomano001's avatar
RRomano001
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7 years ago

This seems an Homework, again schematic is the basic approach to initial learning of FPGA but deprecated, useful if you need convert old discrete logic design.

Your design has error in it and state network nor work on logic nor on simulator.

Previous sentence infer nor on FPGA, check for error and retry.

First error is on top, Q0 must be excited by NOT Q0 not Q3..

Regards