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Altera_Forum's avatar
Altera_Forum
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14 years ago

DDR2 controller fails to generate mem_clk, mem_clk_n, dq, ...

Hi experts,

I'm using DDR2 HPC II in Arria II GX device, and the design is DDR2 reference design downloaded from Altera website.

IP generation, simulation, compiling and downloading bit file are all OK.

And ras_n, cas_n, we_n, addr, ba... are all OK.

But mem_clk, mem_clk_n, dq, dqs and dqsn have no valid output during calibration.

Did I miss anything?

Please help! Thanks!

I'm running Quartus v10.1 on Windows 7 Pro SP1. The FPGA board is customer-designed.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi all,

    I've found the root cause.

    It's because I'm using differential DQS but assigning mem_clk[0] and mem_clk_n[0] to DIFFIO_TX pins. The document says they should be assigned to DIFF_IN or DIFFIO_RX pins in order to use differential DSQ.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The issue still exists in my new board on which mem_clk[0] and mem_clk_n[0] have already been put to a pair of DIFFIO_RX pins (AC22/AC23 on EP2AGX45DF29C6).

    Please help me!
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    It seems OCT causes this problem. When I change the OUTPUT_TERMINATION setting of these pins from "SERIES 50 OHM WITH CALIBRATION" to "SERIES 50 OHM WITHOUT CALIBRATION", everything is OK. mem_clk/mem_clk_n appear and test_complete will be asserted. There are 50ohm calibration resistors connecting to RUP and RDN pin on my custom board.

    I just don't know why. Could somebody explain it?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    It seems OCT causes this problem. When I change the OUTPUT_TERMINATION setting of these pins from "SERIES 50 OHM WITH CALIBRATION" to "SERIES 50 OHM WITHOUT CALIBRATION", everything is OK. mem_clk/mem_clk_n appear and test_complete will be asserted. There are 50ohm calibration resistors connecting to RUP and RDN pin on my custom board.

    I just don't know why. Could somebody explain it?

    --- Quote End ---

    I am facing the same problem ，i am try to solve it,but i wonder where to change the OUTPUT_TERMINATION,could you show me please ! I wonder how was your work going ,is it work later ?:) waiting for your reply! thank you !
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi!

    also I have a similar problem, but with another device. I am using the CycloneIII development kit. I'm trying to use a DDR2 HPCII but the signals "phy_clk" and "mem_clk" are always low and so the "local_init_done".

    The functional simulation, without the calibration, works fine but when I program the FPGA nothing happened.