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Altera_Forum
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14 years ago

DDR2 controller fails to generate mem_clk, mem_clk_n, dq, ...

Hi experts, I'm using DDR2 HPC II in Arria II GX device, and the design is DDR2 reference design downloaded from Altera website. IP generation, simulation, compiling and downloading bit file are...
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Altera_Forum
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11 years ago

Hi!

also I have a similar problem, but with another device. I am using the CycloneIII development kit. I'm trying to use a DDR2 HPCII but the signals "phy_clk" and "mem_clk" are always low and so the "local_init_done".

The functional simulation, without the calibration, works fine but when I program the FPGA nothing happened.