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Altera_Forum
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14 years ago

DDR2 controller fails to generate mem_clk, mem_clk_n, dq, ...

Hi experts, I'm using DDR2 HPC II in Arria II GX device, and the design is DDR2 reference design downloaded from Altera website. IP generation, simulation, compiling and downloading bit file are...
Altera_Forum's avatar
Altera_Forum
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14 years ago

It seems OCT causes this problem. When I change the OUTPUT_TERMINATION setting of these pins from "SERIES 50 OHM WITH CALIBRATION" to "SERIES 50 OHM WITHOUT CALIBRATION", everything is OK. mem_clk/mem_clk_n appear and test_complete will be asserted. There are 50ohm calibration resistors connecting to RUP and RDN pin on my custom board.

I just don't know why. Could somebody explain it?