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Altera_Forum
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14 years ago

DDR2 controller fails to generate mem_clk, mem_clk_n, dq, ...

Hi experts, I'm using DDR2 HPC II in Arria II GX device, and the design is DDR2 reference design downloaded from Altera website. IP generation, simulation, compiling and downloading bit file are...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The issue still exists in my new board on which mem_clk[0] and mem_clk_n[0] have already been put to a pair of DIFFIO_RX pins (AC22/AC23 on EP2AGX45DF29C6).

Please help me!