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Altera_Forum
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14 years ago

DDR2 controller fails to generate mem_clk, mem_clk_n, dq, ...

Hi experts, I'm using DDR2 HPC II in Arria II GX device, and the design is DDR2 reference design downloaded from Altera website. IP generation, simulation, compiling and downloading bit file are...
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Altera_Forum
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14 years ago

Hi all,

I've found the root cause.

It's because I'm using differential DQS but assigning mem_clk[0] and mem_clk_n[0] to DIFFIO_TX pins. The document says they should be assigned to DIFF_IN or DIFFIO_RX pins in order to use differential DSQ.