DDR Memory HI-PHY Pin Assignment Problems (Cyclone V)

Dear Intel

I think I have ran into yet another unexplainable (or not so unexplainable) problem and that has to do with the DQS/DQ groups and the corresponding hi-phy interface layer.

This is the deal: I have (had) a Cyclone V GX Starter Kit that comes with one LP-DDR2 memory IC. I had the plans to create a simple custom memory controller for it. This means, that I wanted to access the DDR memory chip through just the DQ/DQS groups only and not instantiate a full-blown memory controller using the megafunction.

I quickly learnt that it wasn't so straight forward as it looked. I started off with a clean project and instantiate through Verilog HDL modules the hi-phy atoms to shape a bare interface complonent. This worked well for the data DQS groups, the DQS/DQ x8 groups. Then, I got to the command-address bus for the memory. I deducted that this should be driven by a DQS/DQ x16 output group in order to relate all relevant command signals to the primary memory clock that feeds the memory IC clock pin.

This is where trouble started. I learnt that one of the pins on this Cyclone V GX Starter Kit wasn't even in a DQS group to begin with. It was memory IC signal CA6. In the pinout file it seems that for that pin there is no DQ function for that pin (AE9). However, on the board, the AE8 pin had been left unused that does fall within a DQS group. However, I do not want to solder two pins together on the board. Upon examining the pinout file (xls sheet from your site) I noted that this problem goes for *both* sides of the FPGA; the bottom side controller and the topside controller. Also for the topside controller, CA6 is not included in a DQS group. It's the only pin that is not in a DQS group.

Then I left this alone and went on to work on the CA bus driver of the component. This means, I initially tied all pins (12 pieses for CA0 - CA9., CSn and CEn) to the same clock from the hiphy clock buffer.

In the pin planner, I assigned the 12 bus pins to a DQS-16 group. This research was independent from the Cyclone board, just to see whether I could finish the component using pin assignments corresponding to the legend of the pin-planner.

This did not work. The fitter bugged out with various errors about unable to fit DQS-enable atoms in expected locations due to tieing pins to the given clock.

When I split up the 12 pins and spread the across two x8 groups, associating each pin to the respective DQS strobe clock for the x8 group, it worked. But this is not what I wanted. This solution would leave two independent groups, each being clocked by an independent clock. So either one clock would be the memory clock and as far as timing goes, the second set of pins would be time-aligned to its own clock rather than the memory clock.

Then I went like - Ok, so of a DQS x16 groups is not working then we're going to have the fitter perform an auto fit according to the documentation, which states that if one assign the DQS pin only, the fitter will fit corresponding DQ pins to the group the DQS pin belongs to.

This is where things get interesting. The fitter placed the pins and the project now fit successfully, however, the auto-assigned pins did NOT correspond with the pin planner legend graphics for the DQS x16 group. You can see for yourself in the attached screenshot and you can see by loading the attached project and go straight to the pin-planner (do not compile the project). It still has these assignments. I removed the regular data group assignments and left those for the DQS x16 group only.

Then I became a bit disgruntled. And left the project for what it was. I had been thinking about whether to report it or not and decided not to. Yes, I know what's going on. It's NOT Quartus and it's not the competitor though something else instead. May be because the DDR memory was going to give my sonographer project 1.5 hours worth of memory storage of recorded audio, rather than just 5 seconds of recording time using the S-RAM on the starter kit.

Very recently, I decided to look again at my DDR interface project and loading it up. The auto-fitted pins still showed like they were on the screenshot. Again I went through the process of removing all but the DQS clock pin and have the auto-fitter fit again. I did this multiple times because:

-The fitter put the DQ pins in the opposite DQS x16 group, matching the legend.

-The fitter put the DQ pins in the first DQS x16 group, after moving the DQS pin to the opposite group.

Now it supposedly looked like it wasa fitter bug where the DQ pins were auto-placed in the opposing second group contrary to the group the DQS pin was placed in. I know it's not a bug. The random scattering of autoplaced pins as shown in the screenshot could no longer be replicated.

So to finish this report, I am going to say I now understand why you insert this liability notice with regard to downloading and using Quartus for one's projects.

Please use the attached materials for the better. So for I am not able and or allowed to use DDR memory interfaces with Cyclone V chips.

Sincerely,

Arno van Harskamp (The Netherlands)