DDR Memory HI-PHY Pin Assignment Problems (Cyclone V)

Hello Adzim,

Thanks for your reply. You are right, the board has one Micron LPDDR2 4Gb chip on board. It is connected to the bottom side memory controller section of the FPGA which in actual is mounted upside down (bottom side points towards back edge of the board).

I understand that to use the memory I have to connect it using the information supplied with the board. This is what I did when I started a project to use the memory. I include a few screenshots; three show three pages of the Starter Kit user manual, listing all of the LPDDR2 pin locations. The other picture shows part of the Cyclone 5 GX pinout file from Intel. Both show that memory pin CA6 is connected to FPGA pin AE9.

This pin falls outside DQS group 3B, you can see this in the pinout file and the pin planner. THe pinoutfile also shows that the hard-memory controller (HMC) pin CA6 connects to FPGA pin AE9. However, this pin is not inside a DQS group while I think it is supposed to for the memory to work correctly through the hi-speed physical interface. Important to note is that pin AE8 is unconnected on the starter kit board. Pin AE8 is part of DQS group 3B. This suggests that I have to grab an iron and solder pins AE8 and AE9 together and keep AE9 in high-Z and use pin AE8 instead. Also, the CA pins of the memory seem not to be part of a DQS x16 group which means I would have to drive the command bus through 2 DQSx8 groups. That would be alright for this board.

However; I posted two different problems. This was the first problem. The second problem is separate from the kit and is research independent from the kit. The second problem is that fitter auto-place assignments do not match with the pin planner overview / legend. The Cyclone V manual says, if the user places only the DQS differential strobe (positive and negative pin), the fitter will then place all DQ pins associated with the DQS strobe into the same x8 or x16 group. For x16 groups this is not happening and DQ pins were placed randomly and now they are placed in the opposite bottom group; there are two DQS x16 groups at the bottom side.

This typical Cyclone 5 GX seems to support 2 HMC and each driving two separate command busses and 6 separate data channels, counting up to a 2-channel 24-bit memory controller per side, making this chip support 4-channel 24-bit DDR memory which looks like it is optimized for 24-bit DSP applications.

Thank you for your time.

P.S. I don't think something can be fixed and I think something is faulty, though not through Intel or Terasic doing.