DDR Memory HI-PHY Pin Assignment Problems (Cyclone V)

Hello,

I will accept your answer for now; I do not want to get into a fight with Intel over this.

However, I will let you know that you may look for the "ADDCMD" clock source for the cyclonev_clock_phase_select atom in the generated sources when you instantiate the memorycontroller IP mega function. That's where you will find that the cyclonev_hmc atom connects to the ddout atom of a pad which is clocked by the clock wire that is connected to the DQS3B clock pin. Also, the OCT and DLL component are still required; I remember these are instantiated inside the megafunction source as well.

Anyways, you may close the thread and I thank you for your time.