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Arno-NL's avatar
Arno-NL
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2 years ago

DDR Memory HI-PHY Pin Assignment Problems (Cyclone V)

Dear Intel I think I have ran into yet another unexplainable (or not so unexplainable) problem and that has to do with the DQS/DQ groups and the corresponding hi-phy interface layer. This is the de...
Hdl
Arno-NL's avatar
Arno-NL
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Remark: I forgot to mention that the manual pin assignments in the attached screenshot are the copied auto-fitter pin locations. This to make the fitter pin assignments visible in the pin planner. This process was repeated for all of the tests involving the placement of the DQS pin only, where after a fit the locations were copied to make them visible as the maroon circles. This allows one to visualize the mismatch between auto-placement and the legend easily.