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Arno-NL's avatar
Arno-NL
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

DDR Memory HI-PHY Pin Assignment Problems (Cyclone V)

Dear Intel I think I have ran into yet another unexplainable (or not so unexplainable) problem and that has to do with the DQS/DQ groups and the corresponding hi-phy interface layer. This is the de...
Hdl
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello,


I don't think it's need to be placed in DQS group for this device.

Since it's hard memory controller, the placement must be follow on what has been stated in pinout file.

I will not say it's a faulty on this.


For the second problem, I'm not sure if there is any issue in Quartus regarding to the Fitter behavior.

Would you let me know about the Quartus version that has been used?


Regards,

Adzim


  • Arno-NL's avatar
    Arno-NL
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hello Adzim,

    I would like to let you know that I also examined the hard memory controller and the memory controller mega function. I ca tell the HMC and the Hi-PHY IP works together. The latter is the interface part to both the logic fabric but may also be driven by the hard memory controller.

    The Quartus version I have been using is 20.1.1. Please look at the following file of a default Quartus install:

    C:\intelFPGA_lite\20.1\quartus\libraries\megafunctions\xml_info\cyclonev_hmc_info.xml

    This is an info file in XML format that tells what parameters and ports an atom has. This is the atom for the hard memory controller of a Cyclone V.

    When you look at it, you will find a number of ports:

    		<PORT NAME="afiaddr" TYPE="OUTPUT" WIDTH="20" DEFAULT_VALUE="0"/>
		<PORT NAME="aficke" TYPE="OUTPUT" WIDTH="2" DEFAULT_VALUE="0"/>
		<PORT NAME="aficsn" TYPE="OUTPUT" WIDTH="2" DEFAULT_VALUE="0"/>
		<PORT NAME="afidm" TYPE="OUTPUT" WIDTH="10" DEFAULT_VALUE="0"/>
		<PORT NAME="afiodt" TYPE="OUTPUT" WIDTH="2" DEFAULT_VALUE="0"/>
		<PORT NAME="afirdataen" TYPE="OUTPUT" WIDTH="5" DEFAULT_VALUE="0"/>
		<PORT NAME="afirdataenfull" TYPE="OUTPUT" WIDTH="5" DEFAULT_VALUE="0"/>
		<PORT NAME="afiwdata" TYPE="OUTPUT" WIDTH="80" DEFAULT_VALUE="0"/>
		<PORT NAME="afiwdatavalid" TYPE="OUTPUT" WIDTH="5" DEFAULT_VALUE="0"/>

    The port names shown here connect directly to the corresponding atom parts of the hi-phy interface that you can find in my attached project RTL viewer. Pin "afiaddr" is the unpacked CA bus (20 lines) that go to the DDRIO units of the DQS pins Please note that in the pinout file, the clock pin (CLK) connects to DQS3B strobe pin; all other CA pins are part of DQ3B x8 group. Only CA6 is not in a group.

    Hope this helps.

    P.S. I have experience with being ssabotaged / having false information. This is done by a high-stakes third party and not by Intel. I do not say Intel provides false information or sabotages customers. I do not hold respondible Intel.