New ContributorDCFIFO_MIXED_WIDTH simulation incorrect
According to the "FIFO Intel® FPGA IP User Guide", the DCFIFO has a special DCFIFO_MIXED_WIDTHS variant that allows different write and read port widths (ration as powers of 2).
Figure 7 and 8 show write and read transaction for 16 to 8 and 8 to 16 bit interfaces as I'd expect it.
When I instantiate a DCFIFO_MIXED_WIDTHS with Quartus 18.1 (18.1.0 222 or 18.1.2 277) and with those options, the simulation (Questa Sim 64 10.6e - and also Modelsim) doesn't show the expected behaviour though:
For 8 bit write, 16 bit read, the upper 8 bits of the words read are all zeros. In the inverse case, the output word is always the lower part of the input word - and rdusedw and wrusedw also don't behave like in the figures.
I have attached a screenshot of my simulation for the 8 bit write, 16 bit read case.
Are there any special settings to be done when instantiating it via the dcfifo_mixed_widths primitive?
(the target is a Stratix 10, but the same behaviour also shows for the Arria 10 as target)
Thanks in advance, Steffen
