Forum Discussion
SStär
New Contributor
New ContributorDCFIFO_MIXED_WIDTH simulation incorrect
According to the "FIFO Intel® FPGA IP User Guide", the DCFIFO has a special DCFIFO_MIXED_WIDTHS variant that allows different write and read port widths (ration as powers of 2). Figure 7 and 8 show ...
KennyT_altera
Super Contributor
Super ContributorAs long as you are simulating vo or vho files, you are simulating the netlist. It is not under simulation, it is under Quartus assignmnet -> settings.
