Forum Discussion
SStär
New Contributor
New ContributorDCFIFO_MIXED_WIDTH simulation incorrect
According to the "FIFO Intel® FPGA IP User Guide", the DCFIFO has a special DCFIFO_MIXED_WIDTHS variant that allows different write and read port widths (ration as powers of 2). Figure 7 and 8 show ...
KennyT_altera
Super Contributor
Super ContributorHi, what you can do is try on Gate level simulation to see the behavior. If it is intended_device_family, there is a high chance it is not supported.
