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SStär's avatar
SStär
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7 years ago

DCFIFO_MIXED_WIDTH simulation incorrect

According to the "FIFO Intel® FPGA IP User Guide", the DCFIFO has a special DCFIFO_MIXED_WIDTHS variant that allows different write and read port widths (ration as powers of 2). Figure 7 and 8 show ...
SStär's avatar
SStär
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7 years ago

Hi again,

so I have very carefully checked again the settings (generics) when instantiating the dcfifo_mixed_widths and figured that this "feature" is related to the "intended_device_family" generic.

If I set this to "UNUSED", I get the behaviour as described, if I set it to "Arria 10" or "Stratix 10", then the FIFO behaviour is as expected.

Please let me know if that is an intended feature. I aim at a very generic implementation where also the device is set as a generic and might be undeterminded ("UNUSED"), but of course, I'd still like the simulation to show the correct behaviour.

Thanks and tschö, Steffen