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SStär
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7 years ago

DCFIFO_MIXED_WIDTH simulation incorrect

According to the "FIFO Intel® FPGA IP User Guide", the DCFIFO has a special DCFIFO_MIXED_WIDTHS variant that allows different write and read port widths (ration as powers of 2). Figure 7 and 8 show ...
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SStär
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7 years ago

Dear @KennyT_Intel​ ,

so I was checking my Quartus installation up and down, but I don't have this "Generate netlist for functional simulation only" in the settings list.

No matter which Simulation tool name I select, the only 5 settings are "Architecture name in VHDL output netlist", "Bring out device-wide set/reset signals as ports", "Do not write top level VHDL entity", "Flatten buses into individual nodes" and "Truncate long hierarchy paths". These are all set to "Off", except the first which is set to "structure".

I made some further tests for intended_device_family: E.g. setting it to "Cyclone IV" in case I don't know what it will be, seems to work (even if I don't have any Cyclone devices installed.

That is an acceptable work-around for me.

Tschö, Steffen