Forum Discussion
SStär
New Contributor
New ContributorDCFIFO_MIXED_WIDTH simulation incorrect
According to the "FIFO Intel® FPGA IP User Guide", the DCFIFO has a special DCFIFO_MIXED_WIDTHS variant that allows different write and read port widths (ration as powers of 2). Figure 7 and 8 show ...
KennyT_altera
Super Contributor
Super Contributor- To run the functional gate level simulation Click More EDA Netlist Writer Settings. The More EDA Netlist Writer Settings dialog box appears. In the Existing options settings list, click Generate netlist for functional simulation only and select On from the Setting list under Options.
