Data+clk path through (constraints)

Hi,

Im trying to specify timing constraints for a simple design but i dont know how to fully complete the constraints.

I still have unconstrained paths: 'clk_in' and 'clk_out'

report_ucp -panel_name "Unconstrained Paths"

Design is not fully constrained for setup requirements

Design is not fully constrained for hold requirements

The datapath is registered but not the clock path. The datapath seems to be fully constrained but the is still problem with the clock path. (no setup/hold for the "clk_out <= clk <= clk_in" path)

Can anybody help me? Solution/explaination.

Thanks.

Bkirks :)

...see vhdl + sdc here:

<<data_clk_pass_through .vhd .... >>

entity data_clk_pass_through is

port

(

Din : in unsigned (24 downto 0);

Dout : out unsigned (24 downto 0);

clk_in : in std_logic;

clk_out : out std_logic

);

end entity;

architecture rtl of data_clk_pass_through is

signal clk : std_logic;

begin

process (clk)

begin

if (rising_edge(clk)) then

Dout <= Din;

end if;

end process;

clk <= clk_in;

clk_out<=clk;

end rtl;

<<data_clk_pass_through .vhd................. end>>

<<timing.sdc ..........>>

#**************************************************************

# Time Information

#**************************************************************

set_time_format -unit ns -decimal_places 3

#Specify the clock period

set dvi_period 8.000

#*********************************************

#DVI_RX_device (TFP 401)

#Specify the required tSU + tH

set dvi_rx_tSU 2.100

set dvi_rx_tH 0.500

#Boarddelay

set dvi_rx_BD_dmin 0.000

set dvi_rx_BD_dmax 0.000

set dvi_rx_BD_cmin 0.000

set dvi_rx_BD_cmax 0.000

#*********************************************

#*********************************************

#DVI_TX_device (TFP 410)

#Specify the required tSU + tH

set dvi_tx_tSU 1.200

set dvi_tx_tH 1.300

#Boarddelay

set dvi_tx_BD_dmin 0.000

set dvi_tx_BD_dmax 0.000

set dvi_tx_BD_cmin 0.000

set dvi_tx_BD_cmax 0.000

#**********************************************

#**************************************************************

# Create Clock

#**************************************************************

create_clock -name clk_in -period $dvi_period [get_ports {clk_in}]

create_clock -name clk_virtual -period $dvi_period

create_clock -name clk_out -period $dvi_period [get_ports {clk_out}]

#**************************************************************

# Set Input Delay

#**************************************************************

set_input_delay -clock [get_clocks {clk_virtual}] -max [expr $dvi_period - ($dvi_rx_tSU + ($dvi_rx_BD_cmin - $dvi_rx_BD_dmax))] [get_ports {Din*}]

set_input_delay -clock [get_clocks {clk_virtual}] -min [expr $dvi_rx_tH - ($dvi_rx_BD_cmax - $dvi_rx_BD_dmin)] [get_ports {Din*}]

#**************************************************************

# Set Output Delay

#**************************************************************

set_output_delay -clock [get_clocks { clk_out }] -max [expr ($dvi_tx_tSU -($dvi_tx_BD_dmax-$dvi_tx_BD_cmin)) ] [get_ports {Dout*}]

set_output_delay -clock [get_clocks { clk_out }] -min [expr -($dvi_tx_tH -($dvi_tx_BD_cmax-$dvi_tx_BD_dmin)) ] [get_ports {Dout*}]

<<timing.sdc ..........end>>