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Altera_Forum's avatar
Altera_Forum
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13 years ago

Data+clk path through (constraints)

Hi, Im trying to specify timing constraints for a simple design but i dont know how to fully complete the constraints. I still have unconstrained paths: 'clk_in' and 'clk_out' rep...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

you need to treat your output clock as either generated clock or a non clock output.

A generated clock is any clock signal generated by PLL or logic including just wiring as in your case.