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Altera_Forum's avatar
Altera_Forum
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13 years ago

Data+clk path through (constraints)

Hi, Im trying to specify timing constraints for a simple design but i dont know how to fully complete the constraints. I still have unconstrained paths: 'clk_in' and 'clk_out' rep...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

OK, now changed: 

#create_clock -name clk_out -period $dvi_period 
create_generated_clock -name clk_out -source

...but it makes no difference (still same unconstrained paths!!)

clk_in: No input delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment.

clk_out: No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment.