Data+clk path through (constraints)

Hi B_Kirk, in the sdc file under clocks definitions add "derive_clock_uncertainty" command. This will calculate uncertainty between all clocks in design. Maybe this will help.

edit:

you can drive your process and clk_out port directly by clk_in:

--- Quote Start ---

process (clk_in)

begin

if (rising_edge(clk_in)) then

Dout <= Din;

end if;

end process;

clk_out<=clk_in;

--- Quote End ---