CYCLONE V SX, 400Mbps LVDS DDR Interface with DDR or SERDES, timing problems

Hi @cooperd ,

I had checked the design provided. Check this document link https://www.intel.com/content/www/us/en/docs/programmable/683801/current/high-speed-i-o-specifications.html, the max rate for receiver data rate with SERDES factor J =4 to 10 is 640Mbps. Try to set that input data rate from 800Mbps to 600Mbps in order to get clock frequency of 200Mhz. Also, the positive RSKM.

The multicycle path needs one more cycle for example like below (Remember to use same -end/-start for both setup and hold):

set_multicycle_path -from {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|sd*} -to {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|rxreg[*]} -setup -end 3

set_multicycle_path -from {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|sd*} -to {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|rxreg[*]} -hold -end 2

Thanks,

Regards,

Sheng