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CYCLONE V SX, 400Mbps LVDS DDR Interface with DDR or SERDES, timing problems
Hi all, I am struggling and need to know how best to constrain Quartus to fit my design. I am interfacing to a 200Msps, 14 bit ADC using 7 DDR LVDS lines. This makes each LVDS line 400Mbit per sec. First I tried the LVDS SERDES with J=2 but that gave me timing errors as I found out the LVDS SEREDES does not use the dedicated SERDES circuitry for j=1 or 2. So now I am trying J=4 and only using half the bits from the SERDES. I have used the internal pll of the SEREDES and plan to use the clock phase shift to optimise the RSKM I get timing errors no matter what I do. The errors are in the path between the receive buffers and the RX registers and seem to be down to a difference in data paths between the different bits. Device is a CYCLONE V SX speed grade C8. I have tried constraining the design in the sdc file but I do not think I am doing it correctly. Please can anyone help? Thanks Dave Below is the section from my sdc file #************************************************************* # ADC # 1. LVDS SERDES Transmitter/Receiver IP Cores User Guide 683062 | 2017.12.15 # Send Feedback LVDS SERDES Transmitter / Receiver IP Cores User Guide 45 #************************************************************* create_clock -name virtual_clock_lvds -period 5 set_input_delay -clock [get_clocks virtual_clock_lvds] -max 0.5 [get_ports {LVDS_RX[*]}] -add_delay set_input_delay -clock [get_clocks virtual_clock_lvds] -min -0.5 [get_ports {LVDS_RX[*]}] -add_delay # Set false paths to remove irrelevant setup and hold analysis set_false_path -fall_from [get_clocks virtual_clock_lvds] -rise_to [get_clocks ADC_DCLK] -setup set_false_path -rise_from [get_clocks virtual_clock_lvds] -fall_to [get_clocks ADC_DCLK] -setup set_false_path -fall_from [get_clocks virtual_clock_lvds] -rise_to [get_clocks ADC_DCLK] -hold set_false_path -rise_from [get_clocks virtual_clock_lvds] -fall_to [get_clocks ADC_DCLK] -hold # Set multicycle paths as we are running the LVDS at twice the actual data rate to enable Quartus to use the SERDES logic in the FPGA set_multicycle_path -from {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|sd*} -to {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|rxreg[*]} -setup -end 2 set_multicycle_path -from {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|sd*} -to {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|rxreg[*]} -hold -start 21.9KViews0likes5CommentsParts for prototypes
Hi, We are Intel PSG partners and need to be able to get hold of FPGAs for a prototypes for a number of designs we are making right now. None of the parts are available through distribution at present. Please is there someone at Intel we can contact who may help us obtain parts for our prototypes? Thanks Dave894Views0likes4Comments