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SDavi9's avatar
SDavi9
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5 months ago
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Cyclone V & GTS PMA

How do you connect the Cyclone V to the GTS PMA transceiver ?

  • Hi,

    Regarding your inquiry on the example design, for your information, you can generate Direct PHY example design from the Direct PHY IP. You may refer to the "GTS PMA/FEC Direct PHY Intel FPGA IP Example Design" section in the GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs for further details.

    Please feel free to let me know if you have any concern. Thank you.

7 Replies

  • SDavi9's avatar
    SDavi9
    Icon for Occasional Contributor rankOccasional Contributor

    Does such a design exit ? Has anyone had any experience with this ?

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor

    Hi,


    Thank you for filing this case and sharing the details. I appreciate your patience. Please allow me some time to review the information, and I’ll get back to you as soon as possible.


  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor

    Hi,


    Just to keep you posted on the progress. I have been checking through the device datasheets on the TX and RX specs. I am currently clarifying some info with Factory and will keep you posted once received any valid data from them. Thank you.


    • SDavi9's avatar
      SDavi9
      Icon for Occasional Contributor rankOccasional Contributor

      Dear CheePin,

      Thank you for all your help. For the time being I found the following Intel Manuals : GTS Transceiver PHY User Guide Agilex™ 5 FPGAs and SoCs AND the GTS Ethernet Intel® FPGA Hard IP User Guide Agilex™ 5 FPGAs and SoCs and have tried to follow the guidelines there to create a system that can be tested on the Agilex 5 Premium development board. It would be VERY helpful if there was some sort of design example to follow to create the system and to double check what I have done !

      KT

      Shmuel

      • CheepinC_altera's avatar
        CheepinC_altera
        Icon for Regular Contributor rankRegular Contributor

        Hi,

        Regarding your inquiry on the example design, for your information, you can generate Direct PHY example design from the Direct PHY IP. You may refer to the "GTS PMA/FEC Direct PHY Intel FPGA IP Example Design" section in the GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs for further details.

        Please feel free to let me know if you have any concern. Thank you.

    • CheepinC_altera's avatar
      CheepinC_altera
      Icon for Regular Contributor rankRegular Contributor

      Hi,

      Just to keep you informed—based on a review of the datasheets for both the Cyclone V (CV) and Agilex 5 GTS transceivers, there should be no fundamental issues interfacing between the two devices. For your reference, please consult the following sections during your cross-verification:

      Cyclone V Datasheet:
      Transmitter Specifications for GX, GT, SX, and ST Devices
      Receiver Specifications for GX, GT, SX, and ST Devices

      Agilex 5 Datasheet:
      Transmitter Electrical Specifications
      Receiver Electrical Specifications

      It’s generally recommended to use AC coupling to mitigate common-mode voltage mismatches between the devices. Additionally, I suggest performing signal integrity simulations to validate the link performance under your specific operating conditions.

      Let me know if you have any concerns or need further assistance. Thank you.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor

    Hi,


    I believe that your initial question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Altera experts. Otherwise, the community users will continue to help you on this thread. Thank you very much.