Forum Discussion
Occasional ContributorCyclone V & GTS PMA
Hi,
Regarding your inquiry on the example design, for your information, you can generate Direct PHY example design from the Direct PHY IP. You may refer to the "GTS PMA/FEC Direct PHY Intel FPGA IP Example Design" section in the GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs for further details.
Please feel free to let me know if you have any concern. Thank you.
Regular ContributorHi,
Just to keep you posted on the progress. I have been checking through the device datasheets on the TX and RX specs. I am currently clarifying some info with Factory and will keep you posted once received any valid data from them. Thank you.
Occasional ContributorDear CheePin,
Thank you for all your help. For the time being I found the following Intel Manuals : GTS Transceiver PHY User Guide Agilex™ 5 FPGAs and SoCs AND the GTS Ethernet Intel® FPGA Hard IP User Guide Agilex™ 5 FPGAs and SoCs and have tried to follow the guidelines there to create a system that can be tested on the Agilex 5 Premium development board. It would be VERY helpful if there was some sort of design example to follow to create the system and to double check what I have done !
KT
Shmuel
- CheepinC_altera
Hi,
Regarding your inquiry on the example design, for your information, you can generate Direct PHY example design from the Direct PHY IP. You may refer to the "GTS PMA/FEC Direct PHY Intel FPGA IP Example Design" section in the GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs for further details.
Please feel free to let me know if you have any concern. Thank you.
