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Altera_Forum's avatar
Altera_Forum
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17 years ago

Cyclone III SerDes: FPGA to FPGA

Good afternoon people,

I am currently trying to determine if the SERDES capability of the Cyclone III

EP3C120F780 will work for me. The plan is to have a single Cylone III act as a "master" to 3-4 other Altera FPGAs w/LVDS/SerDes capability. The master will transmit 500-600 Mbps serialized data via multi-drop LVDS as well as deserialize responses from the daughter FPGA's.

Since I do not have an actual development kit, nor do I have prototype hardware, I am simulating it via the waveform editor in QII 7.2sp2.

I have attached a test & evaluation project which consists of a simple ALTLVDS_TX and ALTLVDS_RX setup.

What I am doing in the simulation tool is taking the tx_outclock and tx_out of the LVDS transmitter and cutting & pasting it directly as the input for the LVDS receiver. Unfortunately, my data alignment is not looking good.

The ALTLVDS_TX is representative of a transmitting Cyclone III and the ALTLVDS_RX represents a receiving Cyclone III.

Any thoughts, input, design examples?

Thanks in advance,

-Jim

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I don't understand why rx_inclock has a negative timeshift compared to tx_outclock in your simulation, so I don't think that it can be received correctly. Generally, simulations where a design is used as stimulus for another can be better performed with ModelSim. You can e. g. apply variable delay to a signal.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You're right, rx_inclock should be aligned to tx_outclock. I just sim'd it again with the tx_out/rx_in and tx_outclock/rx_inclock signals ALL aligned with respect to each other and my deserialized data is still bit-misaligned.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Apparently, you don't get correct data alignment using the default clock alignment. According to the simulation results, clock phase and bit alignment are both incorrect. I only used devices with DPA capability for receiving source synchronous LVDS data up to now. But I noticed that a Cyclone II example design is available from Altera, it's discussed in the altlvds users guide. I would expect that it's also operational for Cyclone III.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Did you manage to get it solved? I also do use an LVDS connection between 2 CycloneIII fpga's (4 pairs data and 1 clock, deser factor 4... data=16bit 60MHz, ALTLVDS with PLL) and I'm using a syncword of 0000, FFFF, 0000. Simulation in modelsim is everything ok, but in practice I sometimes do not get any sync.

    The PLL is in lock and if I measure on the lvds channels I can recognize the FFFF sync word...

    I'm really interested how you did solved your FPGA - FPFA LVDS connection.