Cyclone III SerDes: FPGA to FPGA

Apparently, you don't get correct data alignment using the default clock alignment. According to the simulation results, clock phase and bit alignment are both incorrect. I only used devices with DPA capability for receiving source synchronous LVDS data up to now. But I noticed that a Cyclone II example design is available from Altera, it's discussed in the altlvds users guide. I would expect that it's also operational for Cyclone III.