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Altera_Forum
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17 years ago

Cyclone III SerDes: FPGA to FPGA

Good afternoon people, I am currently trying to determine if the SERDES capability of the Cyclone III EP3C120F780 will work for me. The plan is to have a single Cylone III act as a "master...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

You're right, rx_inclock should be aligned to tx_outclock. I just sim'd it again with the tx_out/rx_in and tx_outclock/rx_inclock signals ALL aligned with respect to each other and my deserialized data is still bit-misaligned.