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Altera_Forum
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17 years ago

Cyclone III SerDes: FPGA to FPGA

Good afternoon people, I am currently trying to determine if the SERDES capability of the Cyclone III EP3C120F780 will work for me. The plan is to have a single Cylone III act as a "master...
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Altera_Forum
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17 years ago

I don't understand why rx_inclock has a negative timeshift compared to tx_outclock in your simulation, so I don't think that it can be received correctly. Generally, simulations where a design is used as stimulus for another can be better performed with ModelSim. You can e. g. apply variable delay to a signal.