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amildm's avatar
amildm
Icon for Contributor rankContributor
2 years ago
Solved

Cyclone 10 PLLs -> downscale clocks -> how much possible?

Hi All,

I'm working with Cyclone 10 GX, which has a reference clock of 100MHz .
What lowest frequency could I reach with PLLs using this clock as a reference clock?
I've tried to play with Fractional and Integer PLLs and the lowest frequency I succeeded to reach was 3MHz. Is it possible to reach lower frequencies?
How can I set cascading of the PLLs?
Thank you!
  • FvM's avatar
    FvM
    2 years ago
    Hello,
    minimal output frequency is definer bei VCO frequency range and output divider factor. It's about 0.6 MHz. Lower frequencies can be achieved with frequency divider in core logic.

3 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago
    Hello,
    minimal output frequency is definer bei VCO frequency range and output divider factor. It's about 0.6 MHz. Lower frequencies can be achieved with frequency divider in core logic.
  • NazrulNaim_Intel's avatar
    NazrulNaim_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    Thank you for reaching out. Allow me some time to look into your issue. I shall come back to you with findings.


    Thank you for your patience.


    Best Regards,

    Nazrul Naim


  • NazrulNaim_Intel's avatar
    NazrulNaim_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello,


    As per the answer provided by user named 'FvM'. The answer can be accepted. Lower frequencies can be achieved with frequency divider in core logic.


    Regards,

    Nazrul Naim